MRAM is an emerging memory technology, that offer non-volatility, high performance and high endurance. A typical MRAM memory cell includes a magnetic tunnel junction (MTJ) in series with a field effect transistor (FET), which is gated by a word line (WL). A bit line (BL) and a source line (SL) run parallel to each other and perpendicular to the WL. The BL is connected to the MTJ, and the SL is connected to the FET. One memory cell along the BL is selected by turning on its WL. When a relatively large voltage (e.g., 500 mV) is forced across the cell from BL to SL, the selected cell's MTJ is written into a particular state, which is determined by the polarity of this voltage.
When the cell is in a logic “0” or parallel state, its MTJ resistance is lower than when the cell is in a logic “1” or anti-parallel state. A selected cell is read by sensing the resistance from BL to SL. The “sense” or “read” voltage must be much lower than the write voltage in order to clearly distinguish write and read operations, and to avoid inadvertently disturbing the cell during a read operation. Thus, there is a need for sense amplifier (SA) designs capable of sensing very low read voltages (e.g., less than 50 mV).
However, random device variations (e.g., dimensions and other parameters) can lead to an effect, known generally as FET mismatch, which results in random offsets in various circuits, such as pre-amplifiers or other circuits that include FET configurations. To address such offsets, offset-cancellation techniques can be used to minimize the effects of FET mismatch. In a typical offset-cancellation technique applied to an amplifier circuit, during a first phase the amplifier offset is determined and stored on one or more capacitors. The circuit is then re-configured, and during the second phase the capacitors act to cancel out the amplifier offset, ideally resulting in zero offset. In reality, some offset still remains but has been significantly reduced.
In addition, another issue that arises in pre-amplifiers is reference resistance drift. The pre-amplifier compares resistance of a data branch and a reference branch. These resistances include the resistance of MRAM cell (MTJ cell and its FET), and the FETs (P2, N2, and P1, N1) that make up the data branch and the reference branch. Any mismatch between these two resistances will cause the point used to determine logic 0 and 1 to drift.
Accordingly, it is desirable to provide improved MRAM sensing techniques that can reduce the impact of random device variations. It would also be desirable if such MRAM sensing techniques could allow for the size of transistors used in the MRAM sense amplifier to be reduced and/or minimized because larger transistors slow down sensing speed. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.